1. Field of the Invention
The present invention relates to a method to make a marker for double gate SOI processing. Also, the present invention relates to a marker for double gate SOI processing. Moreover, the present invention relates to a semiconductor device provided with such a marker for double gate SOI processing.
2. Description of the Related Technology
Such a marker is known from U.S. Pat. No. 6,335,214 B1 which discloses a SOI (silicon-on-insulator) circuit with double-gate transistors. A method for a double-gate transistor is disclosed wherein a back-side gate is created, which is self-aligned to the upper gate of the transistor.
A transfer method is used to generate marking features on the wafer backside comprising the formation of etch stop spacers on the edge of a gate stack and the etching of an alignment trench through the silicon device layer and through the buried oxide layer, so that deposition of an alignment layer on the bottom of the alignment trench provides a marker on the backside.
Since critical features sizes of semiconductor devices are 100 nm and less, in lithographic processing the requirements for (optical) alignment and overlay are high. In lithographic apparatuses, alignment and overlay detection is performed typically by detecting a plurality of diffracted beams (i.e., diffraction orders) generated by an impinging optical beam on an alignment marker.
Such alignment markers may comprise a grating of which the structure is modified in such a way that the intensity of some selected diffracted beams are biased with respect to the other diffracted beams of which the intensity is relatively reduced.
Due to the biasing of some selected diffraction orders, the diffraction pattern (i.e., the set of diffraction beams) becomes asymmetrical with respect to the impinging optical beam. By this measure the alignment and overlay detection method is generally improved.
However, the asymmetry of alignment signals and their detection in the lithographic apparatus is an obstacle for double gate SOI processing, where wafer bonding is performed. After wafer bonding, further lithographic processing is hindered since the signals generated by the alignment marker can not be detected anymore due to the disturbed asymmetry.